1. Field of the Invention
The present invention relates to a programmable frequency divider. More particularly, the present invention relates to a programmable frequency divider utilizing components to eliminate undesirable output harmonics while reducing overall required circuitry and power consumption.
2. Description of the Related Art
FIG. 1 illustrates a traditional programmable frequency divider 90 that may be employed in a signal synthesizer for dividing the frequency of a sine wave provided by a signal generator 100. The frequency divider of FIG. 1 receives an input signal from a signal generator 100. Typically, the signal generator 100 provides a set of sine wave signals having frequencies that span the range of an octave. For example, the signal generator 100 may provide sine wave signals ranging from 800 Megahertz ("MHZ") to 1600 MHZ.
In order to provide for a broad range of frequency divisions, the programmable frequency divider 90 includes a plurality of divide by two frequency dividers 110.sub.1 -110.sub.n. A first divide by two frequency divider 110.sub.1 is coupled to the signal generator 100 so that its output provides a square wave signal having one half of the frequency of the signal provided by the signal generator 100. The output of the first frequency divider 110.sub.1 is coupled to an input of a second divide by two frequency divider 110.sub.2. The second divide by two frequency divider 110.sub.2 provides a square wave output signal having one fourth of the frequency of the signal provided by the signal generator 100.
The remainder of the plurality of divide by two frequency dividers are all serially connected together in the same manner as described above. As a result, a nth divide by two frequency divider 110.sub.n provides a square wave output signal having a frequency 1/2.sup.n times the frequency of the signal generator's output.
The output of each divide by two frequency divider 110.sub.1-n is coupled to an input of a respective switch 107.sub.1-n. Each switch 107.sub.1-n is programmed to provide an output from one of the divide by two frequency dividers 110.sub.1-n to a respective pair of filters 101.sub.1-n and 102.sub.1-n. The filters 101.sub.1-n, 102.sub.1-n are low pass filters which remove harmonics present at the output of a respective divide by two frequency divider 110.sub.1-n. Each filter 101.sub.1-n, 102.sub.1-n has an output coupled to a respective input of an output switch 113. The output switch 113 enables one of the filter 101.sub.1-n and 102.sub.1-n outputs to be provided on an output 92 of the programmable frequency divider 90.
Two filters are used for each divide by two frequency divider 110.sub.1-n, to enable filtering of all undesirable odd and even harmonics that occur at the frequency divider's 110.sub.1-n output over the entire frequency range of the signal generator 100. If the square wave output provided by a divide by two frequency divider 110.sub.1-n is ideal, the square wave signal has a duty cycle of 50% high time and 50% low time. As a result, the output of the divide by two frequency divider 110.sub.1-n has no even harmonics.
Unfortunately, the slew rate of each frequency divider 110.sub.1-n output typically causes the rising edge of the square wave output to be steeper than the falling edge of the square wave output. This causes the square wave's high times to exceed the low times which results in the presence of even harmonics at each frequency divider 110.sub.1-n output. As the imbalance in the square wave's duty cycle grows, the magnitude of the even harmonics increases.
To illustrate possible signal inputs to the filters 101.sub.1-n and 102.sub.1-n, FIG. 2A shows the frequency domain output of the first frequency divider 110.sub.1 (F.sub.110) in response to an 800 MHZ sine wave input. As shown, the first frequency divider 110.sub.1 output provides a desired 400 MHZ signal along with the following undesirable harmonics: a second harmonic at 800 MHZ, a third harmonic at 1200 MHZ, and further harmonics at multiples of 400 MHZ. FIG. 2B shows the frequency domain output of the first frequency divider 110.sub.1 (F.sub.110) in response to a 1600 MHZ sine wave input. As shown, a desired 800 MHZ signal is provided, along with the following undesirable harmonics: a second harmonic at 1600 MHZ, a third harmonic at 2400 MHZ, and further harmonics at multiples of 800 MHZ. The filters 101.sub.1-n and 102.sub.1-n provide for filtering out the undesirable harmonics. As shown in FIGS. 2A and 2B, an 800 MHZ signal is to be filtered out when the sine wave input to the frequency divider 110.sub.1 is 800 MHZ, and an 800 MHZ signal is to be passed when the sine wave input is 1600 MHZ. Since a single filter cannot both filter out and pass an 800 MHZ signal, filters 101.sub.1 and 102.sub.1 are both employed at the output of divide by two frequency divider 101.sub.1. Filter 101.sub.1 is employed for filtering out undesirable harmonics for a first half of the possible input signal frequencies being provided to frequency divider 110.sub.1. Filter 102.sub.1 is employed for filtering out undesirable harmonics for a second half of the possible input signal frequencies being provided to frequency divider 110.sub.1. Filters 101.sub.2-n and 102.sub.2-n are provided at the outputs of the other frequency dividers 110.sub.2-n to resolve similar dilemmas. When the signal generator 100 provides signals having frequencies in the range of 800 MHZ-1600 MHZ, filter 101.sub.1 is selected by switch 107.sub.1 when the signal generator 100 provides an 800 MHZ-1200 MHZ input signal, and filter 102.sub.1 is selected by switch 107.sub.1 when the signal generator 100 provides an input signal above 1200 MHZ.
The use of multiple divide by two frequency dividers 110.sub.1-n causes the programmable frequency divider 90 of FIG. 1 to occupy a significant amount of circuit board space within a signal synthesizer. The need to employ two low pass filters 101.sub.1-n, 102.sub.1-n and a switch 107.sub.1-n with each divide by two frequency divider 110.sub.1-n further increases the circuit board space required to implement the frequency divider 90 of FIG. 1. Additionally, the use of multiple divide by two frequency dividers 110.sub.1-n and filter sets 101.sub.1-n, 102.sub.1-n causes the frequency divider to consume a significant amount of power when operating in the signal synthesizer.
A signal synthesizer may be employed to detect faults in cables and other communications mediums that are part of an installed communications network. By using a portable signal synthesizer, a field engineer may be able to supply many different test signals to an installed medium at a remote location. However, it is desirable for a portable signal synthesizer to be as small as possible, so that it is easy to transport to remote network installations. It is also desirable for a portable synthesizer to consume as little power as possible, so that it can operate for an extended period of time in the field from the power supplied by a battery. Accordingly, it is desirable for a programmable frequency divider being employed in a portable signal synthesizer to have a reduced amount of circuitry and power consumption.